The pipeline of Fig. 9-2 has the following propagation times: 40 ns for the operands to be read from memory into registers R1 and R2, 45 ns for the signal to propagate through the multiplier, 5 ns for the transfer into R3, and 15 ns to add the two numbers into R5. 

a. What is the minimum clock cycle time that can be used? 

b. A nonpipeline system can perform the same operation by removing R3 and R4. How long will it take to multiply and add the operands without using the pipeline? 

c. Calculate the speedup of the pipeline for 10 tasks and again for 100 tasks. 

d. What is the maximum speedup that can be achieved?

Fig. 9-2

Transcribed Image Text:

AL 모 RI Multiplier R3 B. R2 Adder R5 C₁ R4