Question: Modify the HDL code for the single-cycle MIPS processor, given in Section 7.6.1, to handle one of the new instructions from Exercise 7.3. Enhance the

Modify the HDL code for the single-cycle MIPS processor, given in Section 7.6.1, to handle one of the new instructions from Exercise 7.3. Enhance the testbench, given in Section 7.6.3, to test the new instruction.?

Data from problem 3

Modify the single-cycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.11 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 7.8 to show the changes to the main decoder. Describe any other changes that are required.?

(a) sll?(b) lui(c) slti?(d) blez?

Instruction Opcode R-type 000000 1w 100011 101011 SW beq 000100 Table 7.8

Main decoder truth table to mark up with changes RegWrite RegDst ALUSrc

Instruction Opcode R-type 000000 1w 100011 101011 SW beq 000100 Table 7.8 Main decoder truth table to mark up with changes RegWrite RegDst ALUSrc Branch Mem Write 1 1 0 0 1 1 0 0 0 0 X X 1 0 0 1 0 0 1 0 MemtoReg ALUOP 0 10 1 00 X X 00 01

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