Repeat Exercise 4.48 if the module codel(input logic clk, a, b, c. output logic y): logic x:

Repeat Exercise 4.48 if the <= is replaced by = in every assignment. 

Data from problem 48

Consider the following two SystemVerilog modules. Do they have the same function? Sketch the hardware each one implies. 

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module codel(input logic clk, a, b, c. output logic y): logic x: always_ff @(posedge clk) begin x (= a & b; y <= x | c; end endmodule module code2 (input logic a, b. c. clk, output logic y): logic x; always_ff @(posedge clk) begin y <= x | c: x (= a & b: end endmodule