Repeat Exercise 4.48 if the module codel(input logic clk, a, b, c. output logic y): logic x: always_ff @(posedge clk) begin x (= a &

Repeat Exercise 4.48 if the <= is replaced by = in every assignment. 

Data from problem 48

Consider the following two SystemVerilog modules. Do they have the same function? Sketch the hardware each one implies. 

module codel(input logic clk, a, b, c. output logic y): logic x: always_ff @(posedge clk) begin x (= a & b; y