The following SystemVerilog modules show errors that the authors have seen students make in the laboratory. Explain the error in each module and show how to fix it. 

(a) 

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

(j)

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module latch(input logic clk. input logic [3:0] d. output reg [3:0] q): always @(clk) if (clk) q <= d: endmodule module gates (input logic [3:0] a, b. output logic [3:0] y1. y2. y3. y4. y5): always @(a) begin yl = a & b; y2 = a | b: y3 = a ^ b: y4 =-(a & b): y5 =-(a | b): end endmodule