Write an HDL module for the latch from Figure 3.18. Use one assignment statement for each gate. Specify delays of 1 unit or 1 ns to each gate. Simulate the latch and show that it operates correctly. Then increase the inverter delay. How long does the delay have to be before a race condition causes the latch to malfunction??

CLK D Qorev Q= CLK-D+ CLK-Qprev (prev 1 D- N1 = CLK-D 1 CLK- 1 1 1 1 CLK 1 1 N2 = CLK-Qprev 1 1 1 1 1 1 1 Qprev