You would like to use an FPGA to implement an M&M sorter with a color sensor and motors to put red candy in one jar and green candy in another. The design is to be implemented as an FSM using a Cyclone IV FPGA. According to the data sheet, the FPGA has timing characteristics shown in Table 5.5. You would like your FSM to run at 100 MHz. What is the maximum number of LEs on the critical path? What is the fastest speed at which the FSM will run?

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Table 5.5 Cydone IV timing Name Value (ps) tpegs tecq 199 tyetup 76 thold tpd (per LE) 381 twire (between LEs) 246 tskew