For flip-flop B of Table 15.1 and a 2 GHz clock, check Figure 15.19 for timing violations. If there is a hold violation, indicate where delay must be added, specify the necessary delay, and recheck for setup violations. If there is a setup violation, calculate the maximum error-free frequency.

Data in Figure 15.19

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Logic A tc=10 ps td = 400 ps Logic B t₁ = 100 ps td = 200 ps Logic C t₁ = 30 ps t₁ = 50 ps X Y Z