Question: Write a VHDL test bench for the multiple-of-3 circuit of Exercise 7.7. Data in Exercise 7.7. Write a VHDL description for a circuit that accepts

Write a VHDL test bench for the multiple-of-3 circuit of Exercise 7.7.

Data in Exercise 7.7.

Write a VHDL description for a circuit that accepts a four-bit input and outputs true if the input is a multiple of 3 (3, 6, 9, 12, or 15). Describe why the approach you chose (case, concurrent assignment, structural) is the right approach.

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