(a) Many ISAs have vector extensions where a 32-bit or 64-bit data is treated as four or eight smaller data elements (e.g., bytes or half-words). An add instruction then implicitly accomplishes four or eight adds. Add an instruction to the MIPS processor model shown in Figure 9-8 that adds two 32-bit numbers stored in two general-purpose registers byte by byte, such as RegA[7:0] = RegB[7:0] + RegC[7:0], RegA[15:8] = RegB[15:8] + RegC[15:8], and so forth.
(b) Create a test bench to test this instruction.