(a) Write a model for a D flip-flop with a direct clear input. Use the following timing parameters: t_plh(10 ns), t_phl(10 ns), t_su(5 ns), t_h(3 ns), and t_cmin(20). The minimum allowable clock period is t_cmin. Report appropriate errors if timing violations occur. The timing checks should be done inside: specify …. Endspecify
(b) Write a test bench to test your model. Include tests for every error condition.