A Verilog module has inputs A and B and outputs C and D. A and B are initially high. Whenever A goes low, C will go high 5 ns later, and if A changes again, C will change 5 ns later. D will change if B does not change for 3 ns after A changes. The timing checks should be done inside: specify …. Endspecify 

(a) Write the Verilog module with an always block that determines the outputs C and D.
(b) Write another always block to check that B is stable 2 ns before and 1 ns after A goes high. The always block should also report an error if B goes low for a time interval less than 10 ns.