Consider the following circuit where the combinational circuit is represented by COMB and clock skew is represented by tskew. 

Given the following parameters: 

FF setup time = 10 ns
FF hold time = 2 ns
FF propagation delay =  12 to 20 ns
Tcomb1 = 5 ns to 7 ns
Tcomb2 = 6 ns to 11 ns

(a) What is the minimum clock period with t_skew1 = 0; t_skew2 = 3?
(b) Now set Tcomb1 = 1 to 4 ns. Is there a setup time violation for the middle flip-flop? If no, what is the setup time margin?
(c) Now set Tcomb1 = 1 to 4 ns. Is there a hold-time violation for the middle flip-flop? If no, what is the hold-time margin?
(d) What are the minimum values of t_skew1 and t_skew2 that will fix the violations?
(e) What is the minimum clock period after violations have been fixed?

D QHcomb1-D2 Q2Hcomb2HD3 Q3 fskewl CK CK CK Clock skew2