Draw the hardware obtained if the following code is synthesized:
module reg3 (Q1,Q2,Q3,Q4, A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
always @(posedge CLK)
begin

Q1 = A;
Q2 = Q1;
Q3 = Q2;
Q4 = Q3;
end
endmodule