Draw the hardware obtained if the following two modules are synthesized and describe the differences.
module reg3 (Q1,Q2,Q3,Q4,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
// first
always @(posedge CLK)
begin
Q1 <= A;
Q2 <= Q1;
Q3 <= Q2;
Q4 <= Q3;
end
endmodule

module reg3 (Q1,Q2,Q3,Q4,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
// first -> second
always @(posedge CLK)
begin
Q4 <= Q3;
Q3 <= Q2;
Q2 <= Q1;
Q1 <= A;
end
endmodule