When the following Verilog code is simulated, A is changed to 1 at time 5ns. Make a table that shows all changes in A, B, and D and the times at which they occur through time = 40 ns. 

module Q1F00(A)
inout A;
reg B,C;
wire D;
assign #10 D = A ^ B;
always @(D)
begin
C = ~D;
if(C == 1'b1)
A <= #15 ~A;

B <= D;
end
endmodule