Question: What device does the following Verilog code represent? reg Qtmp; always @(CLK,RST) begin if(RST == 1'b1) Qtmp = 1'b0; else if(CLK == 1'b1 && T

What device does the following Verilog code represent?
reg Qtmp;
always @(CLK,RST)
begin
if(RST == 1'b1)
Qtmp = 1'b0;
else if(CLK == 1'b1 && T == 1'b1)
Qtmp = ~Qtmp;
else

begin
end
Q <= Qtmp;
end

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