Consider the Verilog code in Figure P3.2. Given the relationship between the signals IN and OUT, what is the functionality of the circuit described by the code? Comment on whether or not this code represents a good style to use for the functionality that it represents.

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module problem3_17 (IN, OUT); input [3:0] IN; output reg [3:0] OUT; always @(IN) if (IN == 4'b0101) OUT=4'b0001; else if (IN == 4'b0110) OUT=4'b0010; else if (IN == 4'b0111) OUT=4'b0011; else if (IN == 4'b1001) OUT=4'b0010; else if (IN == 4'b1010) OUT=4'b0100; else if (IN == 4'b1011) OUT=4'b0110; else if (IN == 4'b1101) OUT=4'b0011; else if (IN == 4'b1110) OUT=4'b0110; else if (IN == 4'b1111) OUT=4'b1001; else OUT=4'b0000; endmodule