Create a Verilog module named h6to64 that represents a 6-to-64 binary decoder. Use the treelike structure in Figure 4.16, in which the 6-to-64 decoder is built using nine instances of the h3to8 decoder created in Problem 4.26.

Data From Problem 4.26

Create a Verilog module named if2to4 that represents a 2-to-4 binary decoder using an if-else statement. Create a second module named h3to8 that represents the 3-to-8 binary decoder in Figure 4.15 using two instances of the if2to4 module.

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