Figure 5 4 shows a latch built with NOR gates Draw a similar latch using NAND gates Derive its characteristic table and show its timing diagram R S R Qb S 0 1 0 Qa 0 0 Da Do (a) Circuit 11 12 Qa 13 14 15 SR 16 0 0 1 1 17 0 (c) Timing diagram 1 0 1 (b) Characteristic table QaQb 0 1 1 0 (no change) 01 I 0 0 0 19 10 I IN I I IP I I Time I

Question: Figure 5.4 shows a latch built with NOR gates. Draw a similar latch using NAND gates. Derive its characteristic table and show its timing diagram.

Figure 5.4 shows a latch built with NOR gates. Draw a similar latch using NAND gates. Derive its characteristic table and show its timing diagram.

R S R Qb S 0 1 0 Qa 0 0 Da

R S R Qb S 0 1 0 Qa 0 0 Da Do (a) Circuit 11 12 Qa 13 14 15 SR 16 0 0 1 1 17 0 (c) Timing diagram 1 0 1 (b) Characteristic table QaQb 0/1 1/0 (no change) 01 I 0 0 0 19 10 I IN I I IP I I Time I

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