Repeat Problem 6.30, using the style of code in Figure 6.34.

Data From Problem 6.30

Write Verilog code for the FSM shown in Figure 6.57, using the style of code in Figure 6.29.

Transcribed Image Text:

module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'600, B = 2'b01, C = 2'b10; // Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn=0) y <= A; else case (y) A: if (w) else if (w) else B: C: if (w) else default: endcase endmodule // Define output assign z = (y== C); y<= B; y <= A; y<=C; y <= A; y <= C; y <= A; y <= 2'bxx;