Question: Write Verilog code for the FSM shown in Figure P6.1. Present state Y2Y1 00 01 10 11 Next state w = 0 Y2Y1 10 01

Write Verilog code for the FSM shown in Figure P6.1.

Present state Y2Y1 00 01 10 11 Next state w = 0

Present state Y2Y1 00 01 10 11 Next state w = 0 Y2Y1 10 01 11 10 w = 1 Y2Y1 00 00 01 Output N 0 0 0 1

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