Repeat Problem 6.32, using the style of code in Figure 6.34. Data From Problem 6.32 WriteVerilog code
Question:
Repeat Problem 6.32, using the style of code in Figure 6.34.
Data From Problem 6.32
WriteVerilog code for the FSM shown in Figure 6.58, using the style of code in Figure 6.29.
Transcribed Image Text:
module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'600, B = 2'b01, C = 2'b10; // Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn == 0) y <= A; else case (y) A: if (w) else if (w) else B: endmodule C: if (w) else default: endcase // Define output assign z = (y ==C); y<= B; y <= A; y<=C; y <= A; y<=C; y <= A; y <= 2'bxx;
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Related Book For
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
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