Question: Write Verilog code for the FSM described in Problem 6.12. Data From Problem 6.12. Derive a minimal state table for an FSM that acts as

Write Verilog code for the FSM described in Problem 6.12.

Data From Problem 6.12.

Derive a minimal state table for an FSM that acts as a three-bit parity generator. For every three bits that are observed on the input w during three consecutive clock cycles, the FSM generates the parity bit p = 1 if and only if the number of 1s in the three-bit sequence is odd.

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