Write Verilog code for the FSM described in Problem 6.3. Data From Problem 6.3. Derive the state

Question:

Write Verilog code for the FSM described in Problem 6.3.


Data From Problem 6.3.

Derive the state diagram for an FSM that has an input w and an output z. The machine has to generate z = 1 when the previous four values of w were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are allowed. An example of the desired behavior is 

w : 010111100110011111
z : 000000100100010011

Fantastic news! We've Found the answer you've been seeking!

Step by Step Answer:

Related Book For  book-img-for-question
Question Posted: