Design the following combinational circuits for the Game of PIG datapath given in Figure 6-31:

Figure 6-31

(a) D = 1 comparator.

(b) D ≥ 1100100 comparator.
Use AND gates, OR gates, and inverters. Assume the maximum gate fan-in is four.

Transcribed Image Text:

ENDI SUR LDSU- Binary-to-BCD Code Converter 0000 7-bit Ripple Carry Adder D Parallel Load Reg RSSUR with Sync Reset 2-Digit BCD-to-7 Segment Converter CP DIE 3-bit 1-to-6 Counter 2-Digit LCD Display S R LDTI TR1 EN RESET Binary-to-LED Die Dots Decoder D D> 1100100 D Parallel Load Reg RST1R with Sync Reset DO D1 7-Bit 2-to-1 MUX Die Dot Display 7-bit Ripple Carry Adder Binary-to-BCD Code Converter 2-Digit BCD-to-7 Segment Converter 2-Digit LCD Display -WN LDFP- D D = 1 Comparator FP LDT2EN D Parallel Load Reg RST2 R with Sync Reset D RESET- R TR2 FP Control Registers 7-bit Ripple Carry Adder Binary-to-BCD Code Converter 2-Digit BCD-to-7 Segment Converter 2-Digit LCD Display LDCP MUX 1 0 S DIE1 CPFI CP EN D CP