For a given gate, t PHL = 0.05 ns and t PLH = 0.10 ns. Suppose that


For a given gate, tPHL = 0.05 ns and tPLH = 0.10 ns. Suppose that an inertial delay model is to be developed from this information for typical gate-delay behavior.

(a) Assuming a positive output pulse (LHL), what would the propagation delay and rejection time be?

(b) Discuss the applicability of the parameters in (a) assuming a negative output pulse (HLH).

All HDL iles for circuits referred to in the remaining problems are available in ASCII form for simulation and editing on the Companion Website for the text. A VHDL or Verilog compiler/simulator is necessary for the problems or portions of problems requesting simulation. Descriptions can still be written, however, for many problems without using compilation or simulation.

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Logic And Computer Design Fundamentals

ISBN: 9780133760637

5th Edition

Authors: M. Morris Mano, Charles Kime, Tom Martin

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