Give an example of a sequence of program and data memory read addresses that will have a high hit rate for a unified cache and a low hit rate for separate instruction and data caches. Assume that each of the instruction and data caches is two-way set associative with parameters as in Figure 12-6. Assume that the unified cache is four-way set associative with parameters as in Figure 12-6. Both the instructions and the data are 32-bit words, and the address resolution is to bytes.

Figure 12-6

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Index Tag 00 111111 01 10 11 000001 9 87 6 5 Tag Cache Data 4 3 2 1 Index Byte (a) Memory address Tag 000001 000000 Cache Data Address 0000000000 0000000100 0000001000 0000001100 0000010000 0000010100 0000011000 0000011100 1111100000 1111100100 1111101000 1111101100 1111110000 1111110100 1111111000 1111111100 Data ... Main memory (b) Cache mapping