Give an example of a sequence of program and data memory read addresses that will have a high hit rate for separate instruction and data caches and a low hit rate for a unified cache. Assume direct-mapped caches with the parameters in Figure 12-3. Both the instructions and data are 32-bit words, and the address resolution is to bytes.

Figure 12-3.

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98 7 6 5 4 3 2 1 0 Tag Index Byte Index 000 001 010 011 100 101 110 111 (a) Memory address Tag Data 00000 Cache Address 0000000000 0000000100 0000001000 0000001100 0000010000 0000010100 0000011000 0000011100 1111100000 1111100100 1111101000 1111101100 1111110000 1111110100 1111111000 1111111100 Data : Main memory (b) Cache mapping