The single- cycle computer in Figure 8-15 executes the ive instructions described by the register transfers in the table that follows.

Figure 8-15

(a) Complete the following table, giving the binary instruction decoder outputs from Figure 8-16 during execution of each of the instructions:

Figure 8-16

(b) Complete the following table, giving the instruction in binary for the single-cycle computer that executes the register transfer (if any field is not used, give it the value 0):

Transcribed Image Text:

V- C-Branch N-Control Z PJB LBC PC Extend Address Instruction memory Instruction IR (8:6) || IR (2:0) IR (2:0) Instruction decoder Zero fill DBAMFM RMPJB A A ABSD WWL BC CONTROL Jump Address RW- DA AA - Constant in FS N D Register file A Bus A Bus D B-BA 10 MUX B MD- Bus B Function unit F B MB Address out Data out 01 MUX D DATAPATH MW Data in Address Data memory Data out Data in