Write a gate- level structural Verilog description for the circuit from Problem 4-11. Use the Verilog model for a D lip- lop from Figure 4-33.

Problem 4-11:

A sequential circuit has two D lip- lops, one input X, and one output Y. The logic diagram of the circuit is shown in Figure 4-49. Derive the state table and state diagram of the circuit. 

Figure 4-49:

Figure 4-33:

Transcribed Image Text:

Clock X D C A D B Y