Write a gate- level structural VHDL description for the circuit from Problem 4-11. Use the VHDL model for a D lip- lop from Figure 4-29. Use the package func_prims in library lcdf_vhdl for the logic gate components.

Problem 4-11:

A sequential circuit has two D lip- lops, one input X, and one output Y. The logic diagram of the circuit is shown in Figure 4-49. Derive the state table and state diagram of the circuit.

Figure 4-29:

Clock X- D A D B D Y