Question: Write a Verilog description for the sequential circuit given by the state diagram in Figure 4-19(d). Include an asynchronous RESET signal to initialize the circuit
Write a Verilog description for the sequential circuit given by the state diagram in Figure 4-19(d). Include an asynchronous RESET signal to initialize the circuit to state Init. Compile your description, apply an input sequence to pass through every arc of the state diagram at least once, and verify the correctness of the state and output sequence by comparing them to the state diagram.
Figure 4-19(d):
0/0 or 1/1 0/1 B2= 0 0/0 or 1/1 B3 = X B3=0) 0/1 (BI=0 0/1 1/0 0/1 Init B2 = 1 (d) 1/0 1/0 B1 = 1 0/1 or 1/1 0/0 or 1/1 (B2=X) 1/0 (B3 = 1
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