A half adder is a combinational logic circuit that has two inputs, x and y, and two outputs, s and

c, that are the sum and carry-out, respectively, resulting from the binary addition of x and y.

(a) Design a half adder as a two-level AND-OR circuit.

(b) Show how to implement a full adder, as shown in Figure 6.2a, by using two half adders and external logic gates, as necessary.

(c) Compare the longest logic delay path through the network derived in Part

(b) to that of the logic delay of the adder network shown in Figure 6.2a.

LO1