Now that you have simulated your first VHDL code, your task is to write a VHDL code for a Half Adder. Recall, that a carryout Half adder has two inputs, a, and b and two outputs, sum, and sum carryout. The lab 1 report should comprise of 1) A lab report with the truth table for the half adder 2) The gate level schematic diagram of the half adder 3) The VHDL half adder source code 4) The output wave forms for the half adder