Question: Show a possible control sequence for implementing the instruction MUL R1, R2 on the processor in Figure 7.1. This instruction multiplies the contents of the

Show a possible control sequence for implementing the instruction MUL R1, R2 on the processor in Figure 7.1. This instruction multiplies the contents of the registers R1 and R2, and stores the result in R2. Higher-order bits in the product, if any, are discarded. Suggest additional control signals as needed, and assume that the multiplier is organized as in Figure 6.7.

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