Question: The delay bubble in Figure 8.6 arises because instruction I2 is delayed in the Decode stage. As a result, instructions I3 and I are delayed

The delay bubble in Figure 8.6 arises because instruction I2 is delayed in the Decode stage. As a result, instructions I3 and I are delayed even if they do not depend on either I or 12. Assume that the Decode stage allows two Decode steps to proceed in parallel. Show that the delay bubble can be completely eliminated if the register file also allows two Write steps to proceed in parallel.

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