f the loop exits after executing only two iterations, draw a pipeline diagram for your MIPS code executed on a 2-issue processor shown in Figure 4.69. Assume the processor has perfect branch prediction and can fetch any 2 instructions (not just consecutive instructions in the same cycle). Don't rearrange your instructions and pad with NOP instructions if necessary. Also, assume full forwarding in the pipeline. (Make sure that there is no dependence between the two instructions in the VLIW).

Figure 4.69

Transcribed Image Text:

80000180 Instruction memory 11 Sign- extend Registers Sign- extend MUX XEM u ALU ALU Write data Data memory Address 80000180 Instruction memory 11 Sign- extend Registers Sign- extend MUX XEM u ALU ALU Write data Data memory Address

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