The propagation delay through the combinational circuit in Figure 5.2 is 600 Ps (picoseconds). The registers have a setup time requirement of 50 ps, and the maximum propagation delay from the clock input to the Q outputs is 70 ps.

(a) What is the minimum clock period required for correct operation of this circuit?

(b) Assume that the circuit is reorganized into three stages as in Figure 5.3, such that the combinational circuit in each stage has a delay of 200 ps. What is the minimum clock period in this case?

Reference of Fig.5.2

Transcribed Image Text:

Clock Fiqure 5.2 Register stage A Combinational logic circuit Basic structure for data processing. Register stage B Register stage A Clock Stage 1 Logic circuit Stage 2 Logic circuit Figure 5.3 A hardware structure with multiple stages. Stage 3 Logic circuit Register stage B Clock Fiqure 5.2 Register stage A Combinational logic circuit Basic structure for data processing. Register stage B Register stage A Clock Stage 1 Logic circuit Stage 2 Logic circuit Figure 5.3 A hardware structure with multiple stages. Stage 3 Logic circuit Register stage B

Answer rating: 100% (QA)

a Refer to the sequential circuit in Figure 52 in the textboo... View the full answer