$[10]$ What is the cycle time for a single cycle $($SC$)$ design and for a multi cycle $($MC$)$ design

assuming that memory access takes $500$psec, that ALU operations and ADDs take

$500$psec, that register accesses $($read or write$)$ take $250$psec and that all other operations

$($e$.$g$.$ latch time for buffers, shifting, sign extension, etc.$)$ take no time at all? Be sure to

explain how you derive your cycle times for the two implementations. Create a diagram

showing the per$-$cycle execution of the following code sequence using first, the single

cycle design and second, the multi cycle design, assuming in both cases that execution

begins at time $0.$ Your diagram should clearly label the start times for each and every

cycle.