What is the cycle time for a single cycle (SC) design and for a multi cycle (MC) designassuming that memory access takes 600psec, that ALU operations and ADDs take 500psec, that register accesses (read or write) take 300psec and that all other operations (e.g. latch time for buffers, shifting, sign extension, etc.) take no time at all?Besureto explain how you deriveyour cycle timesfor the two implementations. Create a diagramshowing the per-cycle execution of the following code sequence using first, the single cycle design and second, the multi cycle design, assuming in both cases that execution begins at time 0.Your diagram should clearly label the start times for each and every cycle

.bck:lw $4, 10($8)

add $3, $4, $7

add$6, $3, $5

sw $6, 30($8)

beq $3, $0, bck