1. (15 points) SAME CPU AS IN SAMPLE PROBLEM CHAPTER 4. CPU has a 1 ns clock cycle time. The Li cache (both I$ and D$) hit time = 1 cycle. The miss penalty = 100 cycles for both caches. I$ miss rate = 4%, D$ miss rate = 10%. Load and store are 30% of instructions. We computed the real CPI to 8 cycles/instruction. Answer the following questions: a. (3 points) Compute the required bandwidth (in bytes/s) from the I$: b. (3 points) Compute the required bandwidth (in bytes/s) from the D$ C. (9 points) This CPU has a unified L2 cache (instruction & data) and the block size in both I$ and D$ L1 is 16B. Compute the needed bandwidth from the L2, break it down in instruction and data bandwidth required. (a) required bandwidth from the 1$ (b) required bandwidth from the D$ (c) required bandwidth from L2 for instructions required bandwidth from L2 for data total L2 bandwidth required 1. (15 points) SAME CPU AS IN SAMPLE PROBLEM CHAPTER 4. CPU has a 1 ns clock cycle time. The Li cache (both I$ and D$) hit time = 1 cycle. The miss penalty = 100 cycles for both caches. I$ miss rate = 4%, D$ miss rate = 10%. Load and store are 30% of instructions. We computed the real CPI to 8 cycles/instruction. Answer the following questions: a. (3 points) Compute the required bandwidth (in bytes/s) from the I$: b. (3 points) Compute the required bandwidth (in bytes/s) from the D$ C. (9 points) This CPU has a unified L2 cache (instruction & data) and the block size in both I$ and D$ L1 is 16B. Compute the needed bandwidth from the L2, break it down in instruction and data bandwidth required. (a) required bandwidth from the 1$ (b) required bandwidth from the D$ (c) required bandwidth from L2 for instructions required bandwidth from L2 for data total L2 bandwidth required