1.) [20 points] (Exercise 5.3) For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Offset Tag 31-10 Index 9-4 3-0 a.) [5 points] What is the cache block size (in words)? b.) [5 points] How many entries does the cache have? c.) [10 points] What is the ratio between total bits required for such a cache Implementation (tag + data) over the data storage bits(data)