$1(40$ points$)$ Use the RTL design process to convert the HLSM diagram below to a Datapath and Controller.

$(4$ pts$)$ List all local storage with its size $($number of bits$)$

$(22$ pts$)$ Draw all necessary components for Datapath and $648$ Register file A$.$

Note: Be sure to explicitly list all inputs, outputs along with their respective sizes in your design for each Datapath component.

The register file has only $1$ READ port and $1$ WRITE port. Draw the register file module with appropriate inputs$/$outputs and bit width.

$(14$ pts$)$ Draw. FSM diagram of the controller $($no need to write its Boolean equations$)$

Input: A$[64][8],$ go $(1-$bit$)$

Output: A$[64][8],$ done $(1-$bit$)$