$[15$ points$]$ The following is a $12-$bit carry lookahead adder using carry lookahead logic. C$0$ and all Xi$,$ Yi inputs are available at the start.

a$.[7$ points$]$ Calculate the gate delay for S$9($show your process$).$

b$.[8$ points$]$ To reduce the delay, if you add the second level lookahead block used in the lecture notes, which generates C$4$ and C$8$ through this block, how does the delay for S$9$ change? $($show your process$).$