(40 pts, 10 each) Assume we have a byte-addressable computer (with a word size of 32 bits) that has a small data cache capable of holding eight words. Each cache block consists of only one 32-bit word. When a given program is executed, the processor reads data from the following sequence of hex addresses 3. 320, 324, 3D8, 3DC, 2EC, 190, 194, 320, 324, 348, 34C, 194, 190 This access pattern is repeated four times. a. Assume that the cache is initially empty. Show the contents of the cache at the end of each pass b. c. d. through this loop if a direct mapped cache is used. Compute the hit rate for this example. Repeat part (a) for an associative-mapped cache that uses the LRU replacement algorithm. Repeat part (a) for a two-way set associative cache that uses the LRU replacement algorithm. Now assume that each cache block consists of TWO 32-bit words. Repeat part (c). (40 pts, 10 each) Assume we have a byte-addressable computer (with a word size of 32 bits) that has a small data cache capable of holding eight words. Each cache block consists of only one 32-bit word. When a given program is executed, the processor reads data from the following sequence of hex addresses 3. 320, 324, 3D8, 3DC, 2EC, 190, 194, 320, 324, 348, 34C, 194, 190 This access pattern is repeated four times. a. Assume that the cache is initially empty. Show the contents of the cache at the end of each pass b. c. d. through this loop if a direct mapped cache is used. Compute the hit rate for this example. Repeat part (a) for an associative-mapped cache that uses the LRU replacement algorithm. Repeat part (a) for a two-way set associative cache that uses the LRU replacement algorithm. Now assume that each cache block consists of TWO 32-bit words. Repeat part (c)