1. A CPU has a clock of 2.8 GHz. Half of each clock cycle is for fetching and the other half for execution. a. What is the access time to the primary storage for the CPU with zero wait states? b. How many wait states (cycles) per fetch will the CPU incur if the primary storage is implemented with an access time of 5 ns? c. How many wait states (cycles) per fetch will the CPU incur if the primary storage is implemented with an access time of 10 ns?

2. Compute the data transfer rates for the following storage devices: Storage Device Access Time Data Transfer Unit Data Transfer Rate (MB/sec) Memory (RAM) 2.0 ns 64 bits Magnetic Disk 3.0 us 256 bits Optical Disk 4.0 ms 512 bits

3. Calculate the Cache improvement based on the following data. Show the details of your calculation. Memory/Cache Access Time Cache Hit Memory 10 ns L2 Cache 1.0 ns 60% L3 Cache 5.0 ns 20%