$1.$ A master$-$slave register is shown below with its clock diagram. Assume that all the transistors have the same ON$-$resistance $\backslash ($ R$\_\{$e q$\}\backslash )$; and the nodes $\backslash (\backslash$mathrm$\{$A$\},\backslash$mathrm$\{$B$\},\backslash$mathrm$\{$C$\}\backslash )$ and Q have the same parasitic capacitance of $\backslash ($ C$\_\{$p$\}\backslash ).$ The clock signals $\backslash ($ C L K $\backslash )$ and $\backslash (\backslash$overline$\{$C L K$\}\backslash )$ are skewed and have $\backslash (0-0\backslash )$ and $1-1$ overlapping times of $\backslash ($ t$\_\{0,0\}\backslash )$ and $\backslash ($ t$\_\{1,1\}\backslash ),$ respectively.

$($a$)$ Is this a static or dynamic register? Why?

$($b$)$ Is this a rising$-$ or falling$-$edge triggered register? Why?

$($c$)$ Derive an expression for the setup time of the register.

$($d$)$ Derive an expression for the clock$-$to$-$Q propagation delay.

$($e$)$ Give an expression for the hold time of the register. Explain.

$($f$)$ What is the constraint of $\backslash ($ t$\_\{0,0\}\backslash )$ for this circuit to work properly?

$($g$)$ Does this register have a constant input capacitance? Explain.