1. a. What is the control sequence for execution of the instruction Add R1, R2 including the instruction fetch phase? (Assume single bus architecture) b. Table with microinstructions a. What is the control sequence for execution of the instruction 2. Add 9 (R71), (R6).R1 including the instruction fetch phase? (Assume single bus architecture) b. Table with microinstructions Internal processo bus Control signs PC Address lines Instruction decoder and contra logic MAR Memory bus MDR IR lines Constant 4 RO Select MUX : Add A ALU Sub Rn1) ALU XOR TEMP Z Single-bus organization of the datapath inside a processor