HOMEWORK No$.3$

a$.$ What is the control sequence for execution of the instruction

Add R$1,$ R$2$

including the instruction fetch phase? $($Assume single bus architecture$)$

b$.$ Table with microinstructions

$2.$ a$.$ What is the control sequence for execution of the instruction Add $9($R$7),($R$6),$R$1$

including the instruction fetch phase? $($Assume single bus architecture$)$

b$.$ Table with microinstructions

Figure $7\mathrm{.}1.$ Single$-$bus organization of the datapath inside a proce: