1. a. What is the control sequence for execution of the instruction Add R1, R2 including the instruction fetch phase? (Assume single bus architecture) 2. b. Table with microinstructions a. What is the control sequence for execution of the instruction Add 9 (R71), (R6),R1 including the instruction fetch phase? (Assume single bus architecture) b. Table with microinstructions Memory bus Select ALU control lines PC Address lines MAR MDR Data lines Constant 4 MUX Add A Sub XOR ALU N B Internal processor Carry-in bus Control signals Instruction decoder and control logic IR RO R(n-1) TEMP